Featured Articles

Cooler Master HAF XM reviewed

Cooler Master HAF XM reviewed

Cooler Master introduced the new HAF XM on April 24. The company's HAF series is instantly recognizable, although the XM moniker…

More...
Cedar Trail to last to Q1 2013

Cedar Trail to last to Q1 2013

Intel Cedar Trail, in both the desktop and notebook variants, will most likely remain unchanged until the end of Q1 2013.…

More...
50 percent of next-gen netbooks will be fanless

50 percent of next-gen netbooks will be fanless

Intel has at least two different design kits for different netbook form factors that should revive this category in 2012. Well,…

More...
Galaxy S III preorders hit 9 million

Galaxy S III preorders hit 9 million

Worldwide preorders for Samsung’s new flagship phone have reportedly hit 9 million. According to Korean media, more than 100 carriers are…

More...
EVGA GTX 690 4GB previewed

EVGA GTX 690 4GB previewed

Geforce GTX 690 launched on May 3, but it wasn’t until recently that first batches of cards were shipped to stores.…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Monday, 20 February 2012 16:44

VIA getting into SSD design

Written by Nick Farrell



It is the newest bandwagon to jump on


VIA appears to be thinking that there is money to be made in SSD design.

We got a clue this morning when an outfit called Tensilica sent us a press release saying that VIA has selected Tensilica's Xtensa dataplane processors (DPUs) for a system-on-chip (SOC) design for solid state drives (SSDs). VIA felt that Tensilica's DPUs would provide over four times the performance of competing processors on key algorithms used to benchmark competitive alternatives and went for it.

But what this seems to be telling us is that VIA has worked out that there is shedloads to be made on the back of SSDs Tensilica's DPUs allow designers to customize the IP core, mix both control and signal processing, and add high-bandwidth connectivity to increase performance without increasing the clock speed. For example, designers can use single-cycle bit field manipulation and arithmetic instructions along with multiple simultaneous single-cycle table lookups to achieve over 10 times the efficiency of other processors. This not only increases IOPS, but also significantly reduces the energy consumed and the complexity of the SOC design itself.

Jiin Lai, VIA's CTO is expecting a lot of competition an the SSD market and he thinks there is a significant advantage using Tensilica DPUs to lower the power and increase the throughput of his  products.

Nick Farrell

E-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
blog comments powered by Disqus

To be able to post comments please log-in with Disqus

Facebook activity

Latest Commented Articles

Recent Comments